Collaboration diagram for XgUARTClock:
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Any of these values may be used by the _ioctl() commands UART_SETCLOCKMODE and UART_GETCLOCKMODE. Most drivers require to set the bit rate after modifying the clock mode. In order to avoid unknown clock output frequencies in master mode, set the clock mode to UART_SYNCSLAVE first, than use UART_SETSPEED to select the bit rate and finally switch to UART_SYNCMASTER or UART_NSYNCMASTER.
Defines | |
#define | UART_SYNC |
#define | UART_MASTER |
#define | UART_NCLOCK |
#define | UART_HIGHSPEED |
#define | UART_ASYNC |
Normal asynchronous mode. | |
#define | UART_SYNCSLAVE |
Synchronous slave mode. | |
#define | UART_SYNCMASTER |
Synchronous master mode. | |
#define | UART_NSYNCSLAVE |
Synchronous slave mode, clock negated. | |
#define | UART_NSYNCMASTER |
Synchronous master mode, clock negated. | |
#define | UART_ASYNC_HS |
Asynchronous high speed mode. |
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Asynchronous high speed mode. More deviation sensitive than normal mode, but supports higher speed. |
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Synchronous master mode, clock negated. Similar to UART_SYNCMASTER, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock output. |
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Synchronous slave mode, clock negated. Similar to UART_SYNCSLAVE, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock input. |
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Synchronous master mode. Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock output. |
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Synchronous slave mode. Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock input. |